* FSL IPUv3 Display/FB

The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics
subsystem in an application processor. The goal of the IPU is to provide
comprehensive support for the flow of data from an image sensor or/and to a
display device.

Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC.
Each IPU unit has two display interfaces.

Required properties for IPU:
- bypass_reset :Bypass reset to avoid display channel being.
  stopped by probe since it may start to work in bootloader: 0 or 1.
- compatible : should be "fsl,imx6q-ipu".
- reg : the register address range.
- interrupts : the error and sync interrupts request.
- clocks : the clock sources that it depends on.
- clock-names:  the related clock names.
- resets : IPU reset specifier.  See reset.txt and fsl,imx-src.txt in
  Documentation/devicetree/bindings/reset/ for details.

Example for IPU:
		ipu1: ipu@02400000 {
			compatible = "fsl,imx6q-ipu";
			reg = <0x02400000 0x400000>;
			interrupts = <0 6 0x4 0 5 0x4>;
			clocks = <&clks 130>, <&clks 131>, <&clks 132>,
				 <&clks 39>, <&clks 40>,
				 <&clks 135>, <&clks 136>;
			clock-names = "bus", "di0", "di1",
				      "di0_sel", "di1_sel",
				      "ldb_di0", "ldb_di1";
			resets = <&src 2>;
			bypass_reset = <0>;
		};

Required properties for fb:
- compatible : should be "fsl,mxc_sdc_fb".
- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi".
- mode_str : "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel,
  "1920x1080M@60" for hdmi. Not required for ldb.
- default_bpp : default bits per pixel: 8/16/24/32
- int_clk : use internal clock as pixel clock: 0 or 1
- late_init : to avoid display channel being re-initialized
  as we've probably setup the channel in bootloader: 0 or 1
- interface_pix_fmt : display interface pixel format as below:
	RGB666		IPU_PIX_FMT_RGB666
	RGB565		IPU_PIX_FMT_RGB565
	RGB24		IPU_PIX_FMT_RGB24
	BGR24		IPU_PIX_FMT_BGR24
	GBR24		IPU_PIX_FMT_GBR24
	YUV444		IPU_PIX_FMT_YUV444
	YUYV		IPU_PIX_FMT_YUYV
	UYVY		IPU_PIX_FMT_UYVY
	YVYV		IPU_PIX_FMT_YVYU
	VYUY		IPU_PIX_FMT_VYUY

Required properties for display:
- compatible : should be "fsl,lcd" for lcd panel
- reg : the register address range if necessary to have.
- interrupts : the error and sync interrupts if necessary to have.
- clocks : the clock sources that it depends on if necessary to have.
- clock-names: the related clock names if necessary to have.
- ipu_id : ipu id for the first display device: 0 or 1
- disp_id : display interface id for the first display interface: 0 or 1
- default_ifmt : save as above display interface pixel format for lcd
- pinctrl-names : should be "default"
- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
  IPU connected.
- gpr : the mux controller for the display engine's display interfaces and the display encoder
	(only valid for mipi dsi now).
- disp-power-on-supply : the regulator to control display panel's power.
			(only valid for mipi dsi now).
- resets : the gpio pin to reset the display device(only valid for mipi display panel now).
- lcd_panel : the video mode name for the display device(only valid for mipi display panel now).
- dev_id : the display engine's identity within the system, which intends to replace ipu_id
	   (only valid for mipi dsi now).

Example for IPU:
		ipu1: ipu@02400000 {
			compatible = "fsl,imx6q-ipu";
			reg = <0x02400000 0x400000>;
			interrupts = <0 6 0x4 0 5 0x4>;
			clocks = <&clks 130>, <&clks 131>, <&clks 132>,
				 <&clks 39>, <&clks 40>,
				 <&clks 135>, <&clks 136>;
			clock-names = "bus", "di0", "di1",
				      "di0_sel", "di1_sel",
				      "ldb_di0", "ldb_di1";
			resets = <&src 2>;
			bypass_reset = <0>;
		};

Example for fb:
		fb0 {
			compatible = "fsl,mxc_sdc_fb";
			disp_dev = "ldb";
			interface_pix_fmt = "RGB666";
			mode_str ="LDB-XGA";
			default_bpp = <16>;
			int_clk = <0>;
			late_init = <0>;
			status = "okay";
		};

Required properties for display:
- Common
  - compatible : should be "fsl,lcd" for lcd panel
  - reg : the register address range if necessary to have.
  - interrupts : the error and sync interrupts if necessary to have.
  - clocks : the clock sources that it depends on if necessary to have.
  - clock-names: the related clock names if necessary to have.
  - pinctrl-names : should be "default"
  - pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
		IPU connected.
  - gpr : the mux controller for the display engine's display interfaces and the
	  display encoder (only valid for mipi dsi now).
- LCD, MIPI
  - ipu_id : ipu id for the first display device: 0 or 1
  - disp_id : display interface id for the first display interface: 0 or 1
- LCD
  - default_ifmt : save as above display interface pixel format for lcd
- MIPI
  - disp-power-on-supply : the regulator to control display panel's power.
			   (only valid for mipi dsi now).
  - resets : the gpio pin to reset the display device(only valid for mipi
	     display panel now).
  - lcd_panel : the video mode name for the display device(only valid for mipi
	     display panel now).
  - dev_id : the display engine's identity within the system, which intends to
	     replace ipu_id (only valid for mipi dsi now).

Optional properties for display:
- LVDS Display Bridge (LDB)
  - split-mode : boolean, if present splits the image pixels to output half of
		 them to LVDS channel 0 and the other half to LVDS channel 1.
  - dual-mode : boolean, if present, only LVDS channel 0 should be configured.
		The image will be cloned to both LVDS channels 0 and 1.


LVDS Display Bridge (LDB)
=========================
The LVDS Display Bridge device tree node contains up to two lvds-channel
nodes describing each of the two LVDS encoder channels of the bridge.

LVDS Channel
============
Each LVDS Channel has to contain a display-timings node that describes the
video timings for the connected LVDS display. For detailed information, also
have a look at Documentation/devicetree/bindings/video/display-timing.txt.

Required properties for LVDS channel:
 - reg : should be <0> or <1>
 - crtc : a string that selects the IPU and display interface (DI) to use:
	  "ipu1-di0"
	  "ipu1-di1"
	  "ipu2-di0"
	  "ipu2-di1"
 - fsl,data-mapping : should be "spwg" or "jeida"
                      This describes how the color bits are laid out in the
                      serialized LVDS signal.
 - fsl,data-width : should be <18> or <24>

Optional properties for LVDS channel:
 - primary : boolean, selects a channel as primary.


Example for ldb display:
		ldb@020e0000 {
			status = "okay";
			ext-ref;

			lvds-channel@0 {
				reg = <0>;
				crtc = "ipu1-di0";
				fsl,data-mapping = "spwg";
				fsl,data-width = <18>;
				primary;
				status = "okay";

				display-timings {
					native-mode = <&timing0>;
					timing0: hsd101pfw2 {
						clock-frequency = <45000000>;
						hactive = <1024>;
						vactive = <600>;
						hfront-porch = <0>;
						hback-porch = <0>;
						hsync-len = <176>;
						vback-porch = <0>;
						vfront-porch = <2>;
						vsync-len = <23>;
					};
				};
			};
		};

Example for mipi dsi display:
		mipi_dsi: mipi@021e0000 {
			compatible = "fsl,imx6q-mipi-dsi";
			reg = <0x021e0000 0x4000>;
			interrupts = <0 102 0x04>;
			gpr = <&gpr>;
			clocks = <&clks 138>, <&clks 204>;
			clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
			dev_id = <0>;
			disp_id = <0>;
			lcd_panel = "TRULY-WVGA";
			disp-power-on-supply = <&reg_mipi_dsi_pwr_on>
			resets = <&mipi_dsi_reset>;
			status = "okay";
		};
